The present invention relates to a data processor.
Conventionaly, there has been proposed an information processing system, for example, a video image processing system (Journal of the Institute of Electronics and Communication Engineers of Japan, 85/4, Vol. J68-D, No. 4).
As an example of such a system, an image processing system has been proposed which includes a processor for processing image data and a processor for processing an address of the image data (JP-A-58-215813).
To implement a high-speed image processing system, a high operation speed is required for the arithmetic operation having an operation configuration unique to the image processing; moreover, the access and the transfer of a great amount of data arranged in a 2-dimensional structure must be accomplished at a high speed.
For the implementation of the high-speed operation, there have been proposed a parallel system and a pipeline system.
In the parallel system, many processor elements are operated in a parallel fashion to achieve a high-speed processing.
Although this system has a possibility of a very high speed operation, a great load is imposed on the software controlling the processing, which leads to a problem that the potential capability of the hardware cannot be sufficiently utilized.
On the other hand, the pipeline system has a simple hardware structure and a simple processing control, and hence a high-speed operation can be relatively easily accomplished. However, since the processing speed is substantially proportional to the switching speed of the transistor, the very high speed operation is limited. The processing is also restricted by the pipeline structure, which leads to a problem that the flexibility of the system is reduced. The speed of the data transfer in the parallel system is determined by the method of combining the processor elements and the memory. The combining method is classified into a shared memory type and a network type. Since the image processing handles a great amount of data, the combining method of shared memory type is adopted in many systems. In the pipeline system, the processing and the transfer is mixed, and hence the speed of each stage of the pipeline must be increased.
The high-speed image processing system enables various image processing and the contents of the image processing include not only a simple linear processing but also nonlinear processing such as a conditional branch processing; consequently, the flexible system is required.
However, this system is not sufficient to organically combine a plurality of processors so as to achieve a high-speed processing and a complex, calculation.